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XR21V1414
4-CH FULL-SPEED USB UART
SEPTEMBER 2010 REV. 1.1.0
GENERAL DESCRIPTION
The XR21V1414 (V1414) is an enhanced 4-channel USB Universal Asynchronous Receiver and Transmitter (UART). The USB interface is fully compliant to Full Speed USB 2.0 specification that supports 12 Mbps USB data transfer rate. The USB interface also supports USB suspend, resume and remote wakeup operations. The V1414 operates from an internal 48MHz clock therefore no external crystal/oscillator is required like previous generation UARTs. With the fractional baud rate generator, any baud rate can accurately be generated using the internal 48MHz clock. The large 128-byte TX FIFO and 384-byte RX FIFO of the V1414 helps to optimize the overall data throughput for various applications. The Automatic Transceiver Direction control feature simplifies both the hardware and software for half-duplex RS-485 applications. If required, the multidrop (9-bit) mode with automatic half-duplex transceiver control feature further simplifies typical multidrop RS-485 applications. The V1414 operates from a single 2.97 to 3.63 volt power supply and has 5V tolerant inputs. The V1414 is available in a 48-pin TQFP package. WHQL certified software drivers for Windows 2000, XP, Vista, 7, and CE, as well as Linux and Mac are supported for the XR21V1414. APPLICATIONS
FEATURES
* USB 2.0 Compliant, Full-speed (12 Mbps)
s
Supports USB suspend, resume and remote wakeup operations Data rates up to 12 Mbps Fractional Baud Rate Generator 128 byte TX FIFO 384 byte RX FIFO 7, 8 or 9 data bits 1 or 2 stop bits Odd, even, mark, space, or no parity Automatic Hardware (RTS/CTS or DTR/DSR) Flow Control Automatic Software (Xon/Xoff) Flow Control Multidrop mode Auto Transceiver Enable Half-Duplex mode Selectable GPIO or Modem I/O
* Enhanced Features of each UART
s s s s s s s s
s s s s s
* Internal 48 MHz clock * Single 2.97-3.63V power supply * 5V tolerant inputs * 48-pin TQFP package * Virtual COM Port WHQL certified drivers
s s s s
Windows 2000, XP Vista and 7 Windows CE 4.2, 5.0, 6.0 Linux Mac
* Portable Appliances * External Converters (dongles) * Battery-Operated Devices * Cellular Data Devices * Factory Automation and Process Controls * Industrial applications
Exar Corporation 48720 Kato Road, Fremont CA, 94538 * (510) 668-7000 * FAX (510) 668-7017 * www.exar.com
XR21V1414
4-CH FULL-SPEED USB UART FIGURE 1. XR21V1414 BLOCK DIAGRAM
REV. 1.1.0
3.3V VCC GND
Fractional BRG
128-byte TX FIFO 384-byte RX FIFO
TXA RXA GPIOA5/RTSA# GPIOA4/CTSA# GPIOA3/DTRA# GPIOA2/DSRA# GPIOA1/CDA# GPIOA0/RIA#
Internal Status and Control Registers USBD+ USBDUSB Slave Interface
GPIOs/ Modem IO
UART Channel A TXB RXB GPIOB[5:0]/ModemIO
UART Channel B (Same as Ch A) SDA SCL I 2C Interface
UART Channel C (Same as Ch A)
TXC RXC GPIOC[5:0]/ModemIO TXD RXD GPIOD[5:0]/ModemIO
Internal 48MHz Oscillator
UART Channel D (Same as Ch A)
2
XR21V1414
REV. 1.1.0
4-CH FULL-SPEED USB UART
FIGURE 2. PIN OUT ASSIGNMENT
GPIOD0/RID# TXD RXD GND GND USBDUSBD+ VCC VCC GPIOD5/RTSD# GPIOD4/CTSD# GPIOD3/DTRD#
36 35 34 33 32 31 30 29 28 27 26 25 24 37 38 39 40 41 42 43 44 45 46 47 48 12 3 4 5 6 7 8 23 22 21 20 19 18 17 16 15 14 13 9 10 11 12
SCL SDA GPIOD1/CDD# VCC GND RXA TXA GPIOC0/RIC# GPIOC1/CDC# GPIOC2/DSRC# GPIOC3/DTRC# GPIOC4/CTSC#
XR21V1414 48-TQFP
GPIOC5/RTSC# RXC TXC GPIOA0/RIA# GPIOA1/CDA# GND VCC GPIOA2/DSRA# GPIOA3/DTRA# GPIOB0/RIB# GPIOB1/CDB# GPIOB2/DSRB#
ORDERING INFORMATION
PART NUMBER XR21V1414IM48 PACKAGE 48-pin TQFP OPERATING TEMPERATURE RANGE -40 to +85 C C DEVICE STATUS Active
GND LOWPOWER GPIOD2/DSRD# GND VCC GPIOA5/RTSA# GPIOA4/CTSA# TXB RXB GPIOB5/RTSB# GPIOB4/CTSB# GPIOB3/DTRB#
3
XR21V1414
4-CH FULL-SPEED USB UART
REV. 1.1.0
PIN DESCRIPTIONS
Pin Description
NAME 48-QFN PIN # TYPE DESCRIPTION
UART Channel A Signals RXA 31 I UART Channel A Receive Data or IR Receive Data. This pin has an internal pull-up resistor. Internal pull-up resistor is not disabled during suspend mode. UART Channel A Transmit Data or IR Transmit Data. UART Channel A general purpose I/O or UART Ring-Indicator input (active low) or Remote Wakeup Input (See "Section 1.5.11, Remote Wakeup" on page 14.). This pin has an internal pull-up resistor which is disabled during suspend mode. If using this GPIO as an input, an external pull-up resistor is required to minimize the power consumption in the suspend mode. UART Channel A general purpose I/O or UART Carrier-Detect input (active low). This pin has an internal pull-up resistor which is disabled during suspend mode. If using this GPIO as an input, an external pull-up resistor is required to minimize the power consumption in the suspend mode. UART Channel A general purpose I/O or UART Data-Set-Ready input (active low). See "Section 1.5.5, Automatic DTR/DSR Hardware Flow Control" on page 13. This pin has an internal pull-up resistor which is disabled during suspend mode. If using this GPIO as an input, an external pull-up resistor is required to minimize the power consumption in the suspend mode. UART Channel A general purpose I/O or UART Data-Terminal-Ready output (active low). See "Section 1.5.5, Automatic DTR/DSR Hardware Flow Control" on page 13. This pin has an internal pull-up resistor which is disabled during suspend mode. If using this GPIO as an input, an external pull-up resistor is required to minimize the power consumption in the suspend mode. UART Channel A general purpose I/O or UART Clear-to-Send input (active low). See "Section 1.5.4, Automatic RTS/CTS Hardware Flow Control" on page 12. This pin has an internal pull-up resistor which is disabled during suspend mode. If using this GPIO as an input, an external pull-up resistor is required to minimize the power consumption in the suspend mode. UART Channel A general purpose I/O or UART Request-to-Send output (active low). See "Section 1.5.4, Automatic RTS/CTS Hardware Flow Control" on page 12. This pin has an internal pull-up resistor which is disabled during suspend mode. If using this GPIO as an input, an external pull-up resistor is required to minimize the power consumption in the suspend mode.
TXA GPIOA0/RIA#
30 21
O I/O
GPIOA1/CDA#
20
I/O
GPIOA2/DSRA#
17
I/O
GPIOA3/DTRA#
16
I/O
GPIOA4/CTSA#
7
I/O
GPIOA5/RTSA#
6
I/O
UART Channel B Signals RXB 9 I UART Channel B Receive Data or IR Receive Data. This pin has an internal pull-up resistor. Internal pull-up resistor is not disabled during suspend mode.
4
XR21V1414
REV. 1.1.0
4-CH FULL-SPEED USB UART
Pin Description
NAME TXB GPIOB0/RIB# 48-QFN PIN # 8 15 TYPE O I/O DESCRIPTION UART Channel B Transmit Data or IR Transmit Data. UART Channel B general purpose I/O or UART Ring-Indicator input (active low). This pin has an internal pull-up resistor which is disabled during suspend mode. If using this GPIO as an input, an external pull-up resistor is required to minimize the power consumption in the suspend mode. UART Channel B general purpose I/O or UART Carrier-Detect input (active low). This pin has an internal pull-up resistor which is disabled during suspend mode. If using this GPIO as an input, an external pull-up resistor is required to minimize the power consumption in the suspend mode. UART Channel B general purpose I/O or UART Data-Set-Ready input (active low). See "Section 1.5.5, Automatic DTR/DSR Hardware Flow Control" on page 13. This pin has an internal pull-up resistor which is disabled during suspend mode. If using this GPIO as an input, an external pull-up resistor is required to minimize the power consumption in the suspend mode. UART Channel B general purpose I/O or UART Data-Terminal-Ready output (active low). See "Section 1.5.5, Automatic DTR/DSR Hardware Flow Control" on page 13. This pin has an internal pull-up resistor which is disabled during suspend mode. If using this GPIO as an input, an external pull-up resistor is required to minimize the power consumption in the suspend mode. UART Channel B general purpose I/O or UART Clear-to-Send input (active low). See "Section 1.5.4, Automatic RTS/CTS Hardware Flow Control" on page 12. This pin has an internal pull-up resistor which is disabled during suspend mode. If using this GPIO as an input, an external pull-up resistor is required to minimize the power consumption in the suspend mode. UART Channel B general purpose I/O or UART Request-to-Send output (active low). See "Section 1.5.4, Automatic RTS/CTS Hardware Flow Control" on page 12. This pin has an internal pull-up resistor which is disabled during suspend mode. If using this GPIO as an input, an external pull-up resistor is required to minimize the power consumption in the suspend mode.
GPIOB1/CDB#
14
I/O
GPIOB2/DSRB#
13
I/O
GPIOB3/DTRB#
12
I/O
GPIOB4/CTSB#
11
I/O
GPIOB5/RTSB#
10
I/O
UART Channel C Signals RXC 23 I UART Channel C Receive Data or IR Receive Data. This pin has an internal pull-up resistor. Internal pull-up resistor is not disabled during suspend mode. UART Channel C Transmit Data or IR Transmit Data. UART Channel C general purpose I/O or UART Ring-Indicator input (active low). This pin has an internal pull-up resistor which is disabled during suspend mode. If using this GPIO as an input, an external pull-up resistor is required to minimize the power consumption in the suspend mode.
TXC GPIOC0/RIC#
22 29
O I/O
5
XR21V1414
4-CH FULL-SPEED USB UART Pin Description
NAME GPIOC1/CDC# 48-QFN PIN # 28 TYPE I/O DESCRIPTION UART Channel C general purpose I/O or UART Carrier-Detect input (active low). This pin has an internal pull-up resistor which is disabled during suspend mode. If using this GPIO as an input, an external pull-up resistor is required to minimize the power consumption in the suspend mode. UART Channel C general purpose I/O or UART Data-Set-Ready input (active low). See "Section 1.5.5, Automatic DTR/DSR Hardware Flow Control" on page 13. This pin has an internal pull-up resistor which is disabled during suspend mode. If using this GPIO as an input, an external pull-up resistor is required to minimize the power consumption in the suspend mode. UART Channel C general purpose I/O or UART Data-Terminal-Ready output (active low). See "Section 1.5.5, Automatic DTR/DSR Hardware Flow Control" on page 13. This pin has an internal pull-up resistor which is disabled during suspend mode. If using this GPIO as an input, an external pull-up resistor is required to minimize the power consumption in the suspend mode. UART Channel C general purpose I/O or UART Clear-to-Send input (active low). See "Section 1.5.4, Automatic RTS/CTS Hardware Flow Control" on page 12. This pin has an internal pull-up resistor which is disabled during suspend mode. If using this GPIO as an input, an external pull-up resistor is required to minimize the power consumption in the suspend mode. UART Channel C general purpose I/O or UART Request-to-Send output (active low). See "Section 1.5.4, Automatic RTS/CTS Hardware Flow Control" on page 12. This pin has an internal pull-up resistor which is disabled during suspend mode. If using this GPIO as an input, an external pull-up resistor is required to minimize the power consumption in the suspend mode.
REV. 1.1.0
GPIOC2/DSRC#
27
I/O
GPIOC3/DTRC#
26
I/O
GPIOC4/CTSC#
25
I/O
GPIOC5/RTSC#
24
I/O
UART Channel D Signals RXD 39 I UART Channel D Receive Data or IR Receive Data. This pin has an internal pull-up resistor. Internal pull-up resistor is not disabled during suspend mode. UART Channel D Transmit Data or IR Transmit Data. UART Channel D general purpose I/O or UART Ring-Indicator input (active low). This pin has an internal pull-up resistor which is disabled during suspend mode. If using this GPIO as an input, an external pull-up resistor is required to minimize the power consumption in the suspend mode. UART Channel D general purpose I/O or UART Carrier-Detect input (active low). This pin has an internal pull-up resistor which is disabled during suspend mode. If using this GPIO as an input, an external pull-up resistor is required to minimize the power consumption in the suspend mode.
TXD GPIOD0/RID#
38 37
O I/O
GPIOD1/CDD#
34
I/O
6
XR21V1414
REV. 1.1.0
4-CH FULL-SPEED USB UART
Pin Description
NAME GPIOD2/DSRD# 48-QFN PIN # 3 TYPE I/O DESCRIPTION UART Channel D general purpose I/O or UART Data-Set-Ready input (active low). See "Section 1.5.5, Automatic DTR/DSR Hardware Flow Control" on page 13. This pin has an internal pull-up resistor which is disabled during suspend mode. If using this GPIO as an input, an external pull-up resistor is required to minimize the power consumption in the suspend mode. UART Channel D general purpose I/O or UART Data-Terminal-Ready output (active low). See "Section 1.5.5, Automatic DTR/DSR Hardware Flow Control" on page 13. This pin has an internal pull-up resistor which is disabled during suspend mode. If using this GPIO as an input, an external pull-up resistor is required to minimize the power consumption in the suspend mode. UART Channel D general purpose I/O or UART Clear-to-Send input (active low). See "Section 1.5.4, Automatic RTS/CTS Hardware Flow Control" on page 12. This pin has an internal pull-up resistor which is disabled during suspend mode. If using this GPIO as an input, an external pull-up resistor is required to minimize the power consumption in the suspend mode. UART Channel D general purpose I/O or UART Request-to-Send output (active low). See "Section 1.5.4, Automatic RTS/CTS Hardware Flow Control" on page 12. This pin has an internal pull-up resistor which is disabled during suspend mode. If using this GPIO as an input, an external pull-up resistor is required to minimize the power consumption in the suspend mode.
GPIOD3/DTRD#
48
I/O
GPIOD4/CTSD#
47
I/O
GPIOD5/RTSD#
46
I/O
USB Interface Signals USBD+ USBDI2C Interface Signals SDA 35 OD I2C-controller data input/output (open-drain). An optional external I2C EEPROM can be used to store default configurations upon power-up including the USB Vendor ID and Device ID. See Table 3. A pull-up resisitor (typically 4.7 to 10 KOhms) is required. If an EEPROM is not used, this pin can be used with the SCL pin to select the Remote Wake-up and Power modes. An external pull-up or pull-down resistor is required. See Table 2. I2C-controller serial input clock. An optional external I2C EEPROM can be used to store default configurations upon power-up including the USB Vendor ID and Device ID. See Table 3. A pull-up resisitor (typically 4.7 to 10 KOhms) is required. If an EEPROM is not used, this pin can be used with the SDA pin to select the Remote Wake-up and Power modes. An external pull-up or pull-down resistor is required. See Table 2. 43 42 I/O I/O USB port differential data plus. This pin has a 1.5 K Ohm internal pull-up resistor. USB port differential data minus.
SCL
36
I
7
XR21V1414
4-CH FULL-SPEED USB UART Pin Description
NAME Miscellaneous Signals LOWPOWER 2 O Low power status output. This pin will be asserted whenever the V1414 device is placed into the suspend state. This pin is sampled momentarily at power-up or at any USB bus reset to configure the polarity of the LOWPOWER output during suspend mode. An external (10K) pull-up resistor will cause the LOWPOWER pin to be asserted HIGH during suspend mode. An external (3.3K) pull-down resistor will cause the LOWPOWER pin to be asserted LOW during suspend mode. +3.3V power supply. (Note that all device inputs are 5V tolerant.) Power supply common, ground. 48-QFN PIN # TYPE DESCRIPTION
REV. 1.1.0
VCC GND
5, 18, 33, 44, 45 1, 4, 19, 32, 40, 41
Pwr Pwr
NOTE: Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
8
XR21V1414
REV. 1.1.0
4-CH FULL-SPEED USB UART
1.0 FUNCTIONAL DESCRIPTIONS 1.1 USB interface
The USB interface of the V1414 is compliant with the USB 2.0 Full-Speed Specifications. The USB configuration model presented by the V1414 to the device driver is compatible to the Abstract Control Model of the USB Communication Device Class (CDC-ACM). The V1414 uses the following set of parameters:
* 1 Control Endpoint
s
Endpoint 0 as outlined in the USB specifications
* 1 Configuration is supported * 2 interfaces per UART channel
s s
Each UART channel has a single interrupt endpoint Each UART channel have bulk-in and bulk-out endpoints USB Vendor ID
1.1.1
Exar's USB Vendor ID is 0x04E2. This is the default Vendor ID that is used for the V1414 unless a valid EEPROM is present on the I2C interface signals. If a valid EEPROM is present, the Vendor ID from the EEPROM will be used. 1.1.2 USB Product ID
The default USB Product ID for the V1414 is 0x1414. If a valid EEPROM is present, the Product ID from the EEPROM will be used. 1.2 USB Device Driver
The V1414 device can be used with either a standard CDC-ACM driver or a custom driver. When the CDCACM driver is used, the driver has no knowledge of the V1414 device registers. Because of this, the V1414 device is initialized to the following settings: TABLE 1: V1414 REGISTER DEFAULTS WITH CDC-ACM DRIVER
REGISTER FLOW_CONTROL GPIO_MODE GPIO_DIRECTION GPIO_INT_MASK VALUE 0x01 0x01 0x08 0x30 NOTES Hardware flow control RTS / CTS flow control DTR configured as an output (in addition to RTS which is set by GPIO_MODE) CD and DSR are interrupt sensitive, i.e. can cause a USB interrupt to be generated
9
XR21V1414
4-CH FULL-SPEED USB UART 1.3 I2C Interface
REV. 1.1.0
The I2C interface provides connectivity to an external I2C memory device (i.e. EEPROM) that can be read by the V1414 for configuration. The SDA and SCL are used to specify whether Remote Wakeup and/or Bus Powered configurations are to be supported. These pins are sampled at power-up. The following table describes how Remote Wakeup and Bus Powered support. TABLE 2: REMOTE WAKEUP AND POWER MODES
SDA 1 1 0 0 SCL 1 0 1 0 REMOTE WAKE-UP SUPPORT No No Yes Yes POWER MODE Self-Powered Bus-Powered Self-Powered Bus-Powered
1.3.1
EEPROM Contents
The I2C address should be 0xA0. An EEPROM can be used to override default Vendor IDs and Device IDs, as well as other attributes and maximum power consumption. The EEPROM must contain 8 bytes of data as specified in Table 3 TABLE 3: EEPROM CONTENTS
EEPROM ADDRESS 0 1 2 3 4 5 6 7 CONTENTS Vendor ID (LSB) Vendor ID (MSB) Product ID (LSB) Product ID (MSB) Device Attributes Device Maximum Power Reserved Signature of 0x58 ('X'). If the signature is not correct, the contents of the EEPROM are ignored.
These values are uploaded from the EEPROM to the corresponding USB Standard Device Descriptor or Standard Configuration Descriptor. For details of the USB Descriptors, refer to the USB 2.0 specifications. 1.3.1.1 Vendor ID
The Vendor ID value replaces the idVendor field in the USB Standard Device Descriptor. 1.3.1.2 Product ID
The Product ID value replaces the idProduct field in the USB Standard Device Descriptor. 1.3.1.3 Device Attributes
The Device Attributes value replaces the bmAttributes field in the USB Standard Configuration Descriptor. The default setting in the V1414 device is 0xA0. The bit field definitions are:
* Bit 7 is reserved - set to '1'
10
XR21V1414
REV. 1.1.0
4-CH FULL-SPEED USB UART
* Bit 6 is Self-powered mode - set to '0' for bus-powered, set to '1' for self-powered * Bit 5 is Remote Wakeup support - set to '0' for no support, set to '1' for remote wakeup support * Bit 4:0 are reserved - set to '0'
1.3.1.4 Device Maximum Power The Device Maximum Power value replaces the bMaxPower field in the USB Standard Configuration Descriptor. The value specified is in units of 2 mA. For example, the value 0x2F is decimal 47 or 94 mA. Note that the default bMaxPower of the V1414 device is 94 mA. 1.4 UART Manager
The UART Manager enables/disables each UART including the TX and RX FIFOs for each UART. The UART Manager is located in a separate register block from the 4 UART channels. 1.5 UART
There are 4 enhanced UART channels in the V1414. Each UART channel is independent, therefore, they will need to be initialized and configured independently. Each UART can be configured via USB control transfers from the USB host. At power-up, the V1414 will default to 9600 bps, 8 data bits, no parity bit, 1 stop bit, and no flow control. If a standard CDC driver accesses the V1414, defaults will change. See "Section 1.2, USB Device Driver" on page 9. 1.5.1 Transmitter
The transmitter consists of a 128-byte TX FIFO and a Transmit Shift Register (TSR). Once a bulk-out packet has been received and the CRC has been validated, the data bytes in that packet are written into the TX FIFO of the specified UART channel. Data from the TX FIFO is transferred to the TSR when the TSR is idle or has completed sending the previous data byte. The TSR shifts the data out onto the TX output pin at the data rate defined by the CLOCK_DIVISOR and TX_CLOCK_MASK registers. The transmitter sends the start bit followed by the data bits (starting with the LSB), inserts the proper parity-bit if enabled, and adds the stopbit(s). The transmitter can be configured for 7 or 8 data bits with or without parity or 9 data bits without parity. If 9 bit data is selected without wide mode, the 9th bit will always be '0'. 1.5.1.1 Wide Mode Transmit
When both 9 bit data and wide mode are enabled, two bytes of data must be written. The first byte that is loaded into the TX FIFO are the first 8 bits (data bits 7-0) of the 9-bit data. Bit-0 of the second byte that is loaded into the TX FIFO is bit-8 of the 9-bit data. The data that is transmitted on the TX pin is as follows: start bit, 9-bit data, stop bit. Use the WIDE_MODE register to enable wide mode. 1.5.2 Receiver
The receiver consists of a 384-byte RX FIFO and a Receive Shift Register (RSR). Data that is received in the RSR via the RX pin is transferred into the RX FIFO along with any error tags such as Framing, Parity, Break and Overrun errors. Data from the RX FIFO can be sent to the USB host by sending a bulk-in packet. If the wide mode is not enabled, then 7 or 8 bits of data and optionally a parity bit are transferred to the USB host 1.5.2.1 Wide Mode Receive
In wide mode, the V1414 receives a 7, 8 or 9 bit character and then forwards the character along with 3 associated error bits to the USB host in two bytes. If data is 7 or 8 bits, a parity bit is also received and checked if enabled. If data is 9 bits, no parity is checked. The 9th bit of data is in bit position 0 along with the 3 error bits, break, frame error and overrun error flags in bit positions 1, 2 & 3 respectively. In wide mode, the parity and framing error and break flag are associated with the character that they accompany and the overrun error is tied to the current contents of the entire RX FIFO.
11
XR21V1414
4-CH FULL-SPEED USB UART FIGURE 3. RECEIVE DATA FORMAT
REV. 1.1.0
7 or 8 bit m ode 1st byte 2nd byte 76543210 x x x x OF BP 7 = `0' in 7 bit m ode P=P arity E rror (= `0' if not enabled) B=B reak F = Fram ing E rror O= O verrun E rror x = `0'
9 bit m ode 1st byte 2nd byte 76543210 x x x x OF B 8 B=B reak F = Fram ing E rror O= O verrun E rror x = `0'
Error flags are also available from the ERROR_STATUS register and the interrupt packet, however these flags are historical flags indicating that an error has occurred since the previous read of the status register. Therefore, no conclusion can be drawn as to which specific byte(s) may have contained an actual error in this manner. 1.5.3 GPIO
Each UART has 6 GPIOs. By default, the GPIOs are general purpose I/Os. However, there are few modes that can be enabled to add additional feature such as Auto RTS/CTS Flow control, Auto DTR/DSR Flow Control or Transceiver Enable Control. See Table 14. 1.5.4 Automatic RTS/CTS Hardware Flow Control
GPIO5 and GPIO4 of the UART channel can be enabled as the RTS# and CTS# signals for Auto RTS/CTS flow control when GPIO_MODE[2:0] = '001' and FLOW_CONTROL[2:0] = '001'. Automatic RTS flow control is used to prevent data overrun errors in local RX FIFO by de-asserting the RTS signal to the remote UART. When there is room in the RX FIFO, the RTS pin will be re-asserted. Automatic CTS flow control is used to prevent data overrun to the remote RX FIFO. The CTS# input is monitored to suspend/restart the local transmitter (see Figure 4):
12
XR21V1414
REV. 1.1.0
4-CH FULL-SPEED USB UART
FIGURE 4. AUTO RTS AND CTS FLOW CONTROL OPERATION
Local UART UARTA Receiver FIFO Trigger Reached Auto RTS Trigger Level Transmitter Auto CTS Monitor RXA TXB Remote UART UARTB Transmitter Auto CTS Monitor Receiver FIFO Trigger Reached Auto RTS Trigger Level
RTSA# TXA
CTSB# RXB
CTSA# Assert RTS# to Begin Transmission 1 ON 2 7 ON 3 8 OFF
RTSB#
RTSA# CTSB# TXB
OFF
10 11
ON ON
Data Starts 4 RXA FIFO INTA (RXA FIFO Interrupt) Receive RX FIFO Data Trigger Level 5
6
Suspend
Restart 9
RTS High Threshold
RTS Low Threshold
12
RX FIFO Trigger Level
RTSCTS1
1.5.5
Automatic DTR/DSR Hardware Flow Control
Auto DTR/DSR hardware flow control behaves the same as the Auto RTS/CTS hardware flow control described above except that it uses the DTR# and DSR# signals. For Auto hardware flow control, FLOW_CONTROL[2:0] = '001'. GPIO3 and GPIO2 become DTR# and DSR#, respectively, when GPIO_MODE[2:0] = '010'. 1.5.6 Automatic XON/XOFF Software Flow Control
When software flow control is enabled, the V1414 compares the receive data characters with the programmed Xon or Xoff characters. If the received character matches the programmed Xoff character, the V1414 will halt transmission as soon as the current character has completed transmission. Data transmission is resumed when a received character matches the Xon character. Software flow control is enabled when FLOW_CONTROL[2:0] = '010'. 1.5.7 Multidrop Mode with address matching
The V1414 device has two address matching modes which are also set by the flow control register using modes 3 and 4. These modes are intended for a multi-drop network application. In these modes, the XON_CHAR register holds a unicast address and the XOFF_CHAR holds a multicast address. A unicast address is used by a transmitting master to broadcast an address to all attached slave devices that is intended for only one slave device. A multicast address is used to broadcast an address intended for more than one recipient device. Each attached slave device should have a unique unicast address value stored in the XON_CHAR register, while multiple slaves may have the same multicast adderss stored in the XOFF_CHAR register. An address match occurs when an address byte (9th bit or parity bit is '1') is received that matches the value stored in either the XON_CHAR or XOFF_CHAR register.
13
XR21V1414
4-CH FULL-SPEED USB UART 1.5.7.1 Receiver
REV. 1.1.0
If an address match occurs in either flow control mode 3 or 4, the address byte will not be loaded into the RX FIFO, but all subsequent data bytes will be loaded into the RX FIFO. The UART Receiver will automatically be disabled when an address byte is received that does not match the values in the XON_CHAR or XOFF_CHAR register. 1.5.7.2 Transmitter
In flow control mode 3, the UART transmitter is always enabled, irrespective of the Rx address match. In flow control mode 4, the UART transmitter will only be enabled if there is an Rx address match. 1.5.8 Programmable Turn-Around Delay
By default, the GPIO5/RTS# pin will be de-asserted immediately after the stop bit of the last byte has been shifted. However, this may not be ideal for systems where the signal needs to propagate over long cables. Therefore, the de-assertion of GPIO5/RTS# pin can be delayed from 1 to 15 bit times via the XCVR_EN_DELAY register to allow for the data to reach distant UARTs. 1.5.9 Half-Duplex Mode
Half-duplex mode is enabled when FLOW_CONTROL[3] = 1. In this mode, the UART will ignore any data on the RX input when the UART is transmitting data. 1.5.10 RX FIFO Latency
In normal operation all bulk-in transfers will be of maxPacketSize (64) bytes to improve throughput and to minimize USB host processing. However, in cases where the baud rate is low this may increase latency unacceptably. To compensate, the V1414 device has a low latency mode in which received data bytes will be immediately forwarded at the next BULK_IN packet. The Low Latency mode will be automatically set from a CDC_ACM_IF_SET_LINE_CODING command whenever the baud rate is less than 46921 bps or alternately a custom driver may set the RX_FIFO_LOW_LATENCY register bit to force RX data to be delivered without delay. 1.5.11 Remote Wakeup
If the V1414 device has entered the Suspend state, the GPIO0/RI# pin of the Channel A UART can be used to request that the host exit the Suspend state. A high to low transition on this pin will cause the device to signal a remote wakeup request to the host via a custom driver. Note that the standard CDC-ACM driver does not support this feature. In order for the remote wakeup to work, several things must be properly configured. First, the GPIO0/RI# pin must be configured as an input. Additionally, the V1414 device must have the remote wakeup feature support indicated in the USB attributes - See "Section 1.3, I2C Interface" on page 10. Lastly, the software driver must inform the USB host that the peripheral device supports the remote wake-up feature.
14
XR21V1414
REV. 1.1.0
4-CH FULL-SPEED USB UART
2.0 USB CONTROL COMMANDS The following table shows all of the USB Control Commands that are supported by the V1414. Commands included are standard USB commands, CDC-ACM commands and custom Exar commands. . TABLE 4: SUPPORTED USB CONTROL COMMANDS
NAME DEV GET_STATUS IF GET_STATUS REQUEST TYPE 0x80 0x81 REQUEST 0 0 VALUE 0 0 0 0 0 1-4, 129132 INDEX 0 0 LENGTH 2 2 0 0 Interface: zero DESCRIPTION Device: remote wake-up + self-powered
EP GET_STATUS
0x82
0
0
0
0-4, 129136
0
2
0 Endpoint: halted
DEV CLEAR_FEATURE EP CLEAR_FEATURE
0x00 0x02
1 1
1 0
0 0
0 0-4, 129136
0 0
0 0
0 0
Device remote wake-up
Endpoint halt
DEV SET_FEATURE DEV SET_FEATURE EP SET_FEATURE
0x00 0x00 0x02
3 3 3
1 2 0
00 0 0
0 0 0-4, 129136
0 test 0
0 0 0
0 0 0
Device remote wake-up Test mode
Endpoint halt
SET_ADDRESS GET_DESCRIPTOR
0x00 0x80
5 6
addr 0
0 1
0 0
0 0
0 len LSB len LSB 1 0 1 7 7 0
0 len MSB len MSB 0 0 0 0 0 0 Set the UART baud rate, parity, stop bits, etc. Get the UART baud rate, parity, stop bits, etc. Set UART control lines Device descriptor
GET_DESCRIPTOR
0x80
6
0
2
0
0
Configuration descriptor
GET_CONFIGURATION SET_CONFIGURATION GET_INTERFACE CDC_ACM_IF SET_LINE_CODING CDC_ACM_IF GET_LINE_CODING CDC_ACM_IF SET_CONTROL_LINE_STATE
0x80 0x00 0x81 0x21 0xA1 0x21
8 9 10 32 33 34
0 n 0 0 0 val
0 0 0 0 0 0
0 0 0-7 0, 2, 4, 6 0, 2, 4, 6 0, 2, 4, 6
0 0 0 0 0 0
15
XR21V1414
4-CH FULL-SPEED USB UART TABLE 4: SUPPORTED USB CONTROL COMMANDS
NAME CDC_ACM_IF SEND_BREAK XR_SET_REG REQUEST TYPE 0x21 REQUEST 35 VALUE val LSB val val MSB 0 INDEX 0, 2, 4, 6 0 LENGTH 0 0 DESCRIPTION Send a break for the specified duration Exar custom command: set one 8-bit register val: 8-bit register value register address: see
REV. 1.1.0
0x40
0
regis- block ter
0
0
Table 7 on page 18
block number: see Table 5
on page 16
XR_GETN_REG 0xC0 1 0 0 regis- block count count ter LSB MSB Exar custom register: get count 8-bit registers register address: see
Table 7 on page 18 block number: see Table 5 on page 16
2.1
UART Block Numbers
The table below lists the block numbers for accessing each of the UART channels and the UART Manager.. TABLE 5: CONTROL BLOCKS
BLOCK NAME UART Channel A UART Channel B UART Channel C UART Channel D UART Manager UART Custom BLOCK NUMBER 0 1 2 3 4 0x66 DESCRIPTION The configuration and control registers for UART channel A. The configuration and control registers for UART channel B. The configuration and control registers for UART channel C. The configuration and control registers for UART channel D. The control registers for the UART Manager. The UART Manager enables/disables the TX and RX FIFOs for each UART. Custom UART control registers. Enables / disables for wide mode, low latency mode and custom interrupt packet.
16
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REV. 1.1.0
4-CH FULL-SPEED USB UART
3.0 REGISTER SET DESCRIPTION The internal register set of the V1414 consists of 3 different blocks of registers: the UART Manager, UART registers and UART miscellaneous registers. The UART Manager controls the TX and RX enables and FIFOs of all UART channels. The UART registers configure and control the remaining UART channel functionality with the exception of low latency mode, wide mode and custom interrupt packet enables in the UART custom register block. Registers are accessed only via the USB interface by the XR_SET_REG and XR_GET_REG commands listed in Table 4. The register address offsets are given in Table 6, Table 7 and Table 15, and the register blocks are given in Table 5. 3.1 UART Manager Registers.. TABLE 6: UART MANAGER REGISTERS
ADDRESS 0X10 0X11 0X12 0x13 0X18 0X19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F REGISTER NAME FIFO_ENABLE_CHA FIFO_ENABLE_CHB FIFO_ENABLE_CHC FIFO_ENABLE_CHD RX_FIFO_RESET_CHA RX_FIFO_RESET_CHB RX_FIFO_RESET_CHC RX_FIFO_RESET_CHD TX_FIFO_RESET_CHA TX_FIFO_RESET_CHB TX_FIFO_RESET_CHC TX_FIFO_RESET_CHD BIT-7 0 0 0 0 Bit-7 Bit-7 Bit-7 Bit-7 Bit-7 Bit-7 Bit-7 Bit-7 BIT-6 0 0 0 0 Bit-6 Bit-6 Bit-6 Bit-6 Bit-6 Bit-6 Bit-6 Bit-6 BIT-5 0 0 0 0 Bit-5 Bit-5 Bit-5 Bit-5 Bit-5 Bit-5 Bit-5 Bit-5 BIT-4 0 0 0 0 Bit-4 Bit-4 Bit-4 Bit-4 Bit-4 Bit-4 Bit-4 Bit-4 BIT-3 0 0 0 0 Bit-3 Bit-3 Bit-3 Bit-3 Bit-3 Bit-3 Bit-3 Bit-3 BIT-2 0 0 0 0 Bit-2 Bit-2 Bit-2 Bit-2 Bit-2 Bit-2 Bit-2 Bit-2 BIT-1 RX RX RX RX Bit-1 Bit-1 Bit-1 Bit-1 Bit-1 Bit-1 Bit-1 Bit-1 BIT-0 TX TX TX TX Bit-0 Bit-0 Bit-0 Bit-0 Bit-0 Bit-0 Bit-0 Bit-0
3.1.1
FIFO_ENABLE Registers
Enables the RX FIFO and TX FIFOs. For proper functionality, the UART TX and RX must be enabled in the following order: FIFO_ENABLE_CHx = 0x1 UART_ENABLE = 0x3 FIFO_ENABLE_CHx = 0x3 3.1.2 // Enable TX FIFO // Enable TX and RX of that channel // Enable RX FIFO
RX_FIFO_RESET and TX_FIFO_RESET Registers
Writing a non-zero value to these registers resets the FIFOs.
17
XR21V1414
4-CH FULL-SPEED USB UART 3.2 UART Register Map TABLE 7: UART REGISTERS
ADDRESS
0X00 0X01 0X02 0X03 0X04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A
REV. 1.1.0
REGISTER NAME
Reserved Reserved Reserved UART_ENABLE CLOCK_DIVISOR0 CLOCK_DIVISOR1 CLOCK_DIVISOR2 TX_CLOCK_MASK0 TX_CLOCK_MASK1 RX_CLOCK_MASK0 RX_CLOCK_MASK1 CHARACTER_FORMAT FLOW_CONTROL Reserved Reserved Reserved XON_CHAR XOFF_CHAR Reserved ERROR_STATUS TX_BREAK XCVR_EN_DELAY Reserved Reserved Reserved Reserved GPIO_MODE
BIT-7
0 0 0 0 Bit-7 Bit-15 0 Bit-7 Bit-15 Bit-7 Bit-15 Stop 0 0 0 0 Bit-7 Bit-7 0 Break Status Bit-7 0 0 0 0 0 0
BIT-6
0 0 0 0 Bit-6 Bit-14 0 Bit-6 Bit-14 Bit-6 Bit-14
BIT-5
0 0 0 0 Bit-5 Bit-13 0 Bit-5 Bit-13 Bit-5 Bit-13 Parity
BIT-4
0 0 0 0 Bit-4 Bit-12 0 Bit-4 Bit-12 Bit-4 Bit-12
BIT-3
0 0 0 0 Bit-3 Bit-11 0 Bit-3 Bit-11 Bit-3 Bit-11
BIT-2
0 0 0 0 Bit-2 Bit-10 Bit-18 Bit-2 Bit-10 Bit-2 Bit-10
BIT-1
0 0 0 RX Bit-1 Bit-9 Bit-17 Bit-1 Bit-9 Bit-1 Bit-9
BIT-0
0 0 0 TX Bit-0 Bit-8 Bit-16 Bit-0 Bit-8 Bit-0 Bit-8
Data Bits 0 0 0 0 Bit-4 Bit-4 0 Framing Error Bit-4 0 0 0 0 0 0 GPIO4 GPIO4 GPIO4 GPIO4 GPIO4 0 0 0 0 XCVR Enable Polarity GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 0 0 0 0 HalfDuplex 0 0 0 Bit-3 Bit-3 0 Break Error Bit-3 Flow Control Mode Select 0 0 0 Bit-2 Bit-2 0 0 Bit-2 Delay 0 0 0 0 Mode Select GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 GPIO0 GPIO0 GPIO0 GPIO0 GPIO0 0 0 0 0 0 0 0 Bit-1 Bit-1 0 0 Bit-1 0 0 0 Bit-0 Bit-0 0 0 Bit-0
0 0 0 0 Bit-6 Bit-6 0 Overrun Error Bit-6 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 Bit-5 Bit-5 0 Parity Error Bit-5 0 0 0 0 0 0 GPIO5 GPIO5 GPIO5 GPIO5 GPIO5
0x1B 0x1C 0x1D 0x1E 0x1F
GPIO_DIRECTION GPIO_INT_MASK GPIO_SET GPIO_CLEAR GPIO_STATUS
0 0 0 0 0
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REV. 1.1.0
4-CH FULL-SPEED USB UART
3.3 3.3.1
UART Register Descriptions UART_ENABLE Register Description (Read/Write)
This register enables the UART TX and RX. For proper functionality, the UART TX and RX must be enabled in the following order: FIFO_ENABLE_CHx = 0x1 UART_ENABLE = 0x3 FIFO_ENABLE_CHx = 0x3 UART_ENABLE[0]: Enable UART TX // Enable TX FIFO // Enable TX and RX of that channel // Enable RX FIFO
* Logic 0 = UART TX disabled. * Logic 1 = UART TX enabled.
UART_ENABLE[1]: Enable UART RX
* Logic 0 = UART RX disabled. * Logic 1 = UART RX enabled.
UART_ENABLE[7:2]: Reserved These bits are reserved and should remain '0'. 3.3.2 CLOCK_DIVISOR0, CLOCK_DIVISOR1, CLOCK_DIVISOR2 Register Description (Read/Write)
These registers are used for programming the baud rate. The V1414 uses a 19-bit divisor and 16-bit mask register. Using the internal 48MHz oscillator, the 19-bit divisor is calculated as follows: CLOCK_DIVISOR = Trunc ( 48000000 / Baud Rate ) For example, if the the baud rate is 115200bps, then CLOCK_DIVISOR = Trunc ( 48000000 / 115200 ) = Trunc (416.66667) = 416 CLOCK_DIVISOR0[7:0]: Baud rate clock divisor bits [7:0] CLOCK_DIVISOR1[7:0]: Baud rate clock divisor bits [15:8] CLOCK_DIVISOR2[2:0]: Baud rate clock divisor bits [18:16] CLOCK_DIVISOR2[7:3]: Reserved These bits are reserved and should remain '0'. 3.3.3 TX_CLOCK_MASK0, TX_CLOCK_MASK1 Register Description (Read/Write)
A look-up table is used for the value of the 16-bit TX Clock mask registers. The index of the look-up table is calculated as follows: index = Trunc ( ( ( 48000000 / Baud Rate ) - CLOCK_DIVISOR ) * 32) For example, if the baud rate is 115200bps, then the index will be: index = Trunc ( ( ( 48000000 / 115200 ) - 416 ) * 32) = Trunc (21.3333) = 21 The values for some baud rates to program the TX_CLOCK_MASK registers are listed in Table 8. For baud rates that are not listed, use the index to select TX_CLOCK_MASK register values from Table 9. 3.3.4 RX_CLOCK_MASK0, RX_CLOCK_MASK1 Register Description (Read/Write)
The values for some baud rates to program the RX_CLOCK_MASK registers are listed in Table 8. For baud rates that are not listed, use the same index calculated for the TX_CLOCK_MASK register to select RX_CLOCK_MASK register values from Table 9.
19
XR21V1414
4-CH FULL-SPEED USB UART TABLE 8: CLOCK DIVISOR AND CLOCK MASK VALUES FOR COMMON BAUD RATES
BAUD RATE (BPS) 1200 2400 4800 9600 19200 38400 57600 115200 230400 460800 500000 576000 921600 1000000 1152000 1500000 2000000 2500000 3000000 3125000 3500000 4000000 4250000 6250000 8000000 12000000 CLOCK DIVISOR (DECIMAL) 40000 20000 10000 5000 2500 1250 833 416 208 104 96 83 52 48 41 32 24 19 16 15 13 12 11 7 6 4 TX CLOCK MASK (HEX) 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0912 0x0B6D 0x0912 0x0208 0x0000 0x0912 0x0040 0x0000 0x0B6D 0x0000 0x0000 0x0104 0x0000 0x0492 0x076D 0x0000 0x0122 0x0B6D 0x0000 0x0000 RX CLOCK MASK (HEX) 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0924 0x0B6A 0x0924 0x0040 0x0000 0x0924 0x0000 0x0000 0x0DB6 0x0000 0x0000 0x0108 0x0000 0x0492 0x0BB6 0x0000 0x0224 0x0DB6 0x0000 0x0000
REV. 1.1.0
For baud rates that are not listed in the table above, use the index value calcuated using the formula in "Section 3.3.3, TX_CLOCK_MASK0, TX_CLOCK_MASK1 Register Description (Read/Write)" on page 19 to determine which TX Clock and RX Clock Mask register values to use from Table 9. For the the RX Clock Mask register, there are 2 values listed and would depend on whether the Clock Divisor is even or odd. For even Clock Divisors, use the value from the first column. For odd Clock Divisors, use the value from the last column.
20
XR21V1414
REV. 1.1.0
4-CH FULL-SPEED USB UART
TABLE 9: TX AND RX CLOCK MASK VALUES
INDEX (DECIMAL) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 TX CLOCK MASK (HEX) 0x0000 0x0000 0x0100 0x0020 0x0010 0x0208 0x0104 0x0844 0x0444 0x0122 0x0912 0x0492 0x0252 0x094A 0x052A 0x0AAA 0x0AAA 0x0555 0x0B55 0x06B5 0x05B5 0x0B6D 0x076D 0x0EDD 0x0DDD 0x07BB 0x0F7B 0x0DF7 0x07F7 0x0FDF 0x0F7F 0x0FFF RX CLOCK MASK (HEX) EVEN CLOCK DIVISOR 0x0000 0x0000 0x0000 0x0400 0x0100 0x0040 0x0820 0x0210 0x0110 0x0888 0x0448 0x0248 0x0928 0x04A4 0x0AA4 0x0954 0x0554 0x0AD4 0x0AB4 0x05AC 0x0D6C 0x0B6A 0x06DA 0x0DDA 0x0BBA 0x0F7A 0x0EF6 0x0BF6 0x0FEE 0x0FBE 0x0EFE 0x0FFE RX CLOCK MASK (HEX) ODD CLOCK DIVISOR 0x0000 0x0000 0x0100 0x0020 0x0010 0x0208 0x0108 0x0884 0x0444 0x0224 0x0924 0x0492 0x0292 0x0A52 0x054A 0x04AA 0x0AAA 0x05AA 0x055A 0x0B56 0x06D6 0x0DB6 0x0BB6 0x076E 0x0EEE 0x0DDE 0x07DE 0x0F7E 0x0EFE 0x07FE 0x0FFE 0x0FFD
21
XR21V1414
4-CH FULL-SPEED USB UART 3.3.5 CHARACTER_FORMAT Register Description (Read/Write)
REV. 1.1.0
This register controls the character format such as the word length (7, 8 or 9), parity (odd, even, forced '0', or forced '1') and number of stop bits (1 or 2). CHARACTER_FORMAT[3:0]: Data Bits. TABLE 10: DATA BITS
DATA BITS 7 8 9 CHARACTER_FORMAT[3:0] 0111 1000 1001
All other values for CHARACTER_FORMAT[3:0] are reserved. CHARACTER_FORMAT[6:4]: Parity Mode Select These bits select the parity mode. If 9-bit data mode has been selected, then writing to these bits will not have any effect. In other words, there will not be an additional parity bit. TABLE 11: PARITY SELECTION
BIT-6 0 0 0 0 1 BIT-5 0 0 1 1 0 BIT-4 0 1 0 1 0 PARITY SELECTION No parity Odd parity Even parity Force parity to mark, "1" Force parity to space, "0"
CHARACTER_FORMAT[7]: Stop Bit select This register selects the number of stop bits to add to the transmitted character and how many stop bits to check for in the received character. TABLE 12: STOP BIT SELECTION
BIT-7 0 2 NUMBER OF STOP BITS 1 stop bit 2 stop bits
3.3.6
FLOW_CONTROL Register Description (Read/Write)
These registers select the flow control mode. These registers should only be written to when the UART is disabled. Writing to the FLOW_CONTROL register when the UART is enabled will result in undefined behavior. Note that the FLOW_CONTROL register settings are used in conjunction with the GPIO_MODE register.
22
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REV. 1.1.0
4-CH FULL-SPEED USB UART TABLE 13: FLOW CONTROL MODE SELECTION
FLOW_CONTROL[2:0]: Flow control mode select
MODE 0 1 2 3 4
BIT-2 BIT-1 BIT-0 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0
MODE DESCRIPTION No flow control, no address matching. HW flow control enabled. Auto RTS/CTS or DTR/DSR must be selected by GPIO_MODE. SW flow control enabled Multidrop mode - RX only after address match, TX independent. (Typically used with GPIO_MODE 3) Multidrop mode - RX / TX only after address match. (Typically used with GPIO_MODE 4)
FLOW_CONTROL[3]: Half-Duplex Mode
* Logic 0 = Normal (full-duplex) mode. The UART can transmit and receive data at the same time. * Logic 1 = Half-duplex Mode. In half-duplex mode, any data on the RX pin is ignored when the UART is
transmitting data. FLOW_CONTROL[7:4]: Reserved These bits are reserved and should remain '0'. 3.3.7 XON_CHAR, XOFF_CHAR Register Descriptions (Read/Write)
The XON_CHAR and XOFF_CHAR registers store the XON and XOFF characters, respectively, that are used in the Automatic Software Flow control. XON_CHAR[7:0]: XON Character In Automatic Software Flow control mode, the UART will resume data transmission when the XON character has been received. For behavior in the Address Match mode, see "Section 1.5.7, Multidrop Mode with address matching" on page 13. For behavior in the Address Match with TX Flow Control mode, see "Section 1.5.7, Multidrop Mode with address matching" on page 13. XOFF_CHAR[7:0]: XOFF Character In Automatic Software Flow control mode, the UART will suspend data transmission when the XOFF character has been received. For behavior in the Address Match mode, see "Section 1.5.7, Multidrop Mode with address matching" on page 13. For behavior in the Address Match with TX Flow Control mode, see "Section 1.5.8, Programmable TurnAround Delay" on page 14.
23
XR21V1414
4-CH FULL-SPEED USB UART 3.3.8 ERROR_STATUS Register Description - Read-only
REV. 1.1.0
This register reports any errors that may have occurred on the line such as break, framing, parity and overrun. ERROR_STATUS[2:0]: Reserved These bits are reserved. Any values read from these bits should be ignored. ERROR_STATUS[3]: Break error
* Logic 0 = No break condition * Logic 1 = A break condition has been detected (clears after read).
ERROR_STATUS[4]: Framing Error
* Logic 0 = No framing error * Logic 1 = A framing error has been detected (clears after read). A framing error occurs when a stop bit is not
present when it is expected. ERROR_STATUS[5]: Parity Error
* Logic 0 = No parity error * Logic 1 = A parity error has been detected (clears after read).
ERROR_STATUS[6]: Overrun Error
* Logic 0 = No overrun error * Logic 1 = An overrun error has been detected (clears after read). An overrun error occurs when the RX FIFO
is full and another byte of data is received. ERROR_STATUS[7]: Break Status
* Logic 0 = Break condition is no longer present. * Logic 1 = Break condition is currently being detected.
3.3.9 TX_BREAK Register Description (Read/Write) Writing a non-zero value to this register causes a break condition to be generated continuously until the register is cleared. If data is being shifted out of the TX pin, the data will be completely shifted out before the break condition is generated. 3.3.10 XCVR_EN_DELAY Register Description (Read/Write)
XCVR_EN_DELAY[3:0]: Turn-around delay This is the number of bit times to wait before changing the direction of the transceiver from transmit to receive when half-duplex mode is enabled. XCVR_EN_DELAY[3:0]: Reserved These bits are reserved and should be '0'.
24
XR21V1414
REV. 1.1.0
4-CH FULL-SPEED USB UART GPIO_MODE Register Description (Read/Write)
3.3.11
GPIO_MODE[2:0]: GPIO Mode Select There are 4 modes of operation for the GPIOs. The descriptions can be found in "Section 1.5, UART" on page 11. TABLE 14: GPIO MODES
BITS [2:0] 000 001 010 011 100 GPIO0 GPIO0 GPIO0 GPIO0 GPIO0 GPIO0 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 GPIO2 GPIO2 GPIO2 DSR# GPIO2 GPIO2 GPIO3 GPIO3 GPIO3 DTR# GPIO3 GPIO3 GPIO4 GPIO4 CTS# GPIO4 GPIO4 GPIO4 GPIO5 GPIO5 RTS# GPIO5 XCVR Enable XCVR Enable MODE DESCRIPTION GPIO Mode, All GPIO pins available as GPIO GPIO4 and GPIO5 used for Auto RTS/CTS HW Flow Control GPIO2 and GPIO3 used for Auto DTR/DSR HW Flow Control GPIO5 used for Auto Transceiver Enable during Transmit GPIO5 used for Auto Transceiver Enable after address match (See FLOW_CONTROL mode 4).
GPIO_MODE[3]: Transceiver Enable Polarity
* Logic 0 = Low for TX * Logic 1 = High for TX
GPIO_MODE[7:4]: Reserved These register bits are reserved. When writing to these bits, the value should be '0'. When reading from these bits, they are undefined and should be ignored. 3.3.12 GPIO_DIRECTION Register Description (Read/Write)
This register controls the direction of the GPIO if it is not controlled by the GPIO_MODE register. GPIO_DIRECTION[5:0]: GPIOx Direction
* Logic 0 = GPIOx is an input. * Logic 1 = GPIOx is an output.
GPIO_DIRECTION[7:6]: Reserved These register bits are reserved and should be '0'. 3.3.13 GPIO_INT_MASK Register Description (Read/Write)
Enables / disables generation of a USB interrupt packet at the change of state of GPIO pins when they are configured as inputs. GPIO_INT_MASK[5:0]: GPIOx Interrupt Mask
* Logic 0 = A change on this input causes the device to generate an interrupt packet. * Logic 1 = A change on this input does not cause the device to generate an interrupt packet.
GPIO_INT_MASK[7:6]: Reserved These register bits are reserved and should be '0'.
25
XR21V1414
4-CH FULL-SPEED USB UART 3.3.14 GPIO_SET Register Description (Read/Write)
REV. 1.1.0
Writing a '1' in this register drives the GPIO output high. Writing a '0' to a bit has no effect. Bits 7-6 are unused and should be '0'. 3.3.15 GPIO_CLEAR Register Description (Read/Write)
Writing a '1' in this register drives the GPIO output low. Writing a '0' to a bit has no effect. Bits 7-6 are unused and should be '0'. 3.3.16 GPIO_STATUS Register Description (Read-Only)
This register reports the current state of the GPIO pin.
3.4
UART Custom Registers TABLE 15: UART CUSTOM REGISTERS
ADDRESS 0X03 0X04
REGISTER NAME UART CHAN A CUSTOM UART CHAN A LOW_LATENCY UART CHAN A CUSTOM_INT_PACKET UART CHAN B CUSTOM UART CHAN B LOW_LATENCY UART CHAN B CUSTOM_INT_PACKET UART CHAN C CUSTOM UART CHAN C LOW_LATENCY UART CHAN C CUSTOM_INT_PACKET UART CHAN D CUSTOM UART CHAN D LOW_LATENCY UART CHAN D CUSTOM_INT_PACKET
BIT-7 0
BIT-6 0
BIT-5 0
BIT-4 0
BIT-3 0
BIT-2 0
BIT-1
BIT-0
MaxPkt- WIDE_E Size N 0 EN
0
0
0
0
0
0
0X06
0
GPIO5
GPIO4
GPIO3
GPIO0
0
GPIO2
GPIO1
0X0B 0X0C 0X0E
0 0
0 0
0 0
0 0
0 0
0 0
MaxPkt- WIDE_E Size N 0 EN
0
GPIO5
GPIO4
GPIO3
GPIO0
0
GPIO2
GPIO1
0X13 0X14
0
0
0
0
0
0
MaxPkt- WIDE_E Size N 0 EN
0
0
0
0
0
0
0X16
0
GPIO5
GPIO4
GPIO3
GPIO0
0
GPIO2
GPIO1
0X1B 0X1C
0
0
0
0
0
0
MaxPkt- WIDE_E Size N 0 EN
0
0
0
0
0
0
0X1E
0
GPIO5
GPIO4
GPIO3
GPIO0
0
GPIO2
GPIO1
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XR21V1414
REV. 1.1.0
4-CH FULL-SPEED USB UART WIDE_MODE Register Description (Read/Write)
3.4.1
This register enables the Wide mode functionality for the UART. WIDE_MODE[0]: Enable wide mode
* Logic 0 = Normal (7, 8 or 9 bit data) mode * Logic 1 = Wide mode - See "Section 1.5.1.1, Wide Mode Transmit" on page 11 and "Section 1.5.2.1,
Wide Mode Receive" on page 11. WIDE_MODE[7:1]: Reserved These bits are reserved and should remain '0'. 3.4.2 LOW_LATENCY Register Description (Read/Write)
This register is automatically set to logic '1' for baud rates below 46921 bps, and can be manually set for baud rates of 46921 bps and higher. This register enables the Low latency feature of the UART. Write to this register following any desired baud rate setting change. LOW_LATENCY[0]: Enable Low Latency mode
* Logic 0 = Receive data is not forwarded from the Rx FIFO until bMaxPacketSize (64 bytes) or timeout (3
characters) has occurred.
* Logic 1 = All data in the RX FIFO is provided to the USB host at the next BULK IN request irrespective of the
number of bytes in the FIFO. LOW_LATENCY[7:1]: Reserved These bits are reserved and should remain '0'. 3.4.3 CUSTOM_INT_PACKET (Read/Write)
This register is used to enable / disable GPIO status in the high data byte of the custom interrupt packet. See Table 16, "Interrupt Packet Format," on page 28 and Table 18, "Data Field of Customized Interrupt Packet Exar Vendor Specific," on page 29. CUSTOM_INT_PACKET[0]: GPIO1
* Logic 0 = Disable GPIO1 status in custom interrupt packet. * Logic 1 = Enable GPIO1 status in custom interrupt packet.
CUSTOM_INT_PACKET[1]: GPIO2
* Logic 0 = Disable GPIO2 status in custom interrupt packet. * Logic 1 = Enable GPIO2 status in custom interrupt packet.
CUSTOM_INT_PACKET[2]: Reserved
* This bit is reserved and should remain '0'.
CUSTOM_INT_PACKET[3]: GPIO0
* Logic 0 = Disable GPIO0 status in custom interrupt packet. * Logic 1 = Enable GPIO0 status in custom interrupt packet.
CUSTOM_INT_PACKET[4]: GPIO3
* Logic 0 = Disable GPIO3 status in custom interrupt packet. * Logic 1 = Enable GPIO3 status in custom interrupt packet.
CUSTOM_INT_PACKET[5]: GPIO4
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4-CH FULL-SPEED USB UART
REV. 1.1.0
* Logic 0 = Disable GPIO4 status in custom interrupt packet. * Logic 1 = Enable GPIO4 status in custom interrupt packet.
CUSTOM_INT_PACKET[6]: GPIO5
* Logic 0 = Disable GPIO5 status in custom interrupt packet. * Logic 1 = Enable GPIO5 status in custom interrupt packet.
CUSTOM_INT_PACKET[7]: Reserved This bit is reserved and should remain '0'. TABLE 16: INTERRUPT PACKET FORMAT
OFFSET 0 FIELD bmRequestType SIZE (BYTES) 1 VALUE 8'b10100001 DESCRIPTION D7 = Device-to-host direction D6:5 = Class Type D4-0: = Interface Recipient Defined encoding for SERIAL_STATE
1 2 4
bNotification wValue wIndex
1 2 2
8'h20 16'h0000 16'h0000
D15-8 = Reserved (0) D7-0 = Interface number, 8'h00 for the CDC Command Interface 2 bytes of transferred data D15-7 = Reserved (0) D6 = bOverRun D5 = bParity D4 = bFraming D3 = bRingSignal (RI) D2 = bBreak D1 = bTxCarrier (DSR) D0 = bRxCarrier (CD)
6 8
wLength Data
2 2
16'h0002 Standard int_status (See Table 17 or Table 18)
TABLE 17: DATA FIELD OF STANDARD INTERRUPT PACKET
BIT(S) D15..D7 D6 D5 D4 D3 D2 D1 D0 bOverRun bParity bFraming bRingSignal bBreak bTxCarrier bRxCarrier FIELD Reserved (0) Received data has been discarded due to overrun in the device. A parity error has occured. A framing error has occured. State of ring signal detection of the device. State of break detection mechanism of the device. State of transmission carrier. This signal corresponds to V.24 signal 106 and RS-232 signal DSR. State of receiver carrier detection mechanism of device. This signal corresponds to V.24 signal 109 and RS-232 signal DCD. DESCRIPTION
28
XR21V1414
REV. 1.1.0
4-CH FULL-SPEED USB UART
If the Exar vendor specific packet mapping is enabled then the data field also includes status for all of the UART / GPIO pins as follows: TABLE 18: DATA FIELD OF CUSTOMIZED INTERRUPT PACKET - EXAR VENDOR SPECIFIC
BIT(S) 15 FIELD D15 Reserved (0) DESCRIPTION
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
bGPIO5 (RTS) bGPIO4 (CTS) bGPIO3 (DTR) bGPIO0 (RI) Reserved (0) bGPIO2 (DSR) bGPIO1 (CD) Reserved (0) bOverRun bParity bFraming bRingSignal (RI) bBreak bTxCarrier (DSR) bRxCarrier (CD)
29
XR21V1414
4-CH FULL-SPEED USB UART 4.0 ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS - POWER CONSUMPTION UNLESS OTHERWISE NOTED: TA = -40O TO +85OC, VCC IS 2.97 TO 3.63V
SYMBOL ICC ISusp PARAMETER MIN Power Supply Current Suspend mode Current LIMITS 3.3V TYP 16 2 UNITS MAX 20 2.15 mA mA CONDITIONS
REV. 1.1.0
DC ELECTRICAL CHARACTERISTICS - UART, LOWPOWER & GPIO PINS UNLESS OTHERWISE NOTED: TA = -40O TO +85OC, VCC IS 2.97 TO 3.63V
SYMBOL VIL VIH VOL VOH IIL IIH CIN PARAMETER MIN Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input Low Leakage Current Input High Leakage Current Input Pin Capacitance 2.2 10 10 5 -0.3 2.0 LIMITS 3.3V MAX 0.8 5.5 0.3 V V V V uA uA pF IOL = 4 mA IOH = -4 mA UNITS CONDITIONS
DC ELECTRICAL CHARACTERISTICS - USB I/O PINS UNLESS OTHERWISE NOTED: TA = -40O TO +85OC, VCC IS 2.97 TO 3.63V
SYMBOL VIL VIH VOL VOH VDrvZ IOSC PARAMETER MIN Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Driver Output Impedance Open short current Current -0.3 2.0 0 2.8 28 LIMITS 3.3V MAX 0.8 5.5 0.3 3.6 44 35 V V V V Ohms mA 1.5 V on USBD+ and USBDExternal 15 K Ohm to GND on USBD- pin External 15 K Ohm to GND on USBD- pin UNITS CONDITIONS
30
XR21V1414
REV. 1.1.0
4-CH FULL-SPEED USB UART
PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1 mm)
D D1 36 25
37
24
D1
D
48
13
1 B A2 e
1 2
C A Seating Plane A1 L
Note: The control dimension is the millimeter column INCHES SYMBOL A A1 A2 B C D D1 e L a MIN 0.039 0.002 0.037 0.007 0.004 0.346 0.272 MAX 0.047 0.006 0.041 0.011 0.008 0.362 0.280 MILLIMETERS MIN 1.00 0.05 0.95 0.17 0.09 8.80 6.90 0.50 BSC 0.45 0x 0.75 7x MAX 1.20 0.15 1.05 0.27 0.20 9.20 7.10
0.020 BSC 0.018 0x 0.030 7x
31
XR21V1414
4-CH FULL-SPEED USB UART REVISION HISTORY
DATE June 2009 September 2010 REVISION 1.0.0 1.1.0 Released Datasheet. Clarified pin functionality, wide mode and low latency mode including registers / blocks, clarified FLOW_CONTROL and GPIO_MODE register functionality. DESCRIPTION
REV. 1.1.0
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2009 EXAR Corporation Datasheet September 2010. Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
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